archivos_practica

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top_system1.vhdlibrary ieee;
use ieee.std_logic_1164.all;
entity top_system1 is
 port(
 CLK : in std_logic;
 RST : in std_logic;
 ASTRB : in std_logic;
 DSTRB : in std_logic;
 DATA : inout std_logic_vector(7 downto 0);
 PWRITE : in std_logic;
 PWAIT : out std_logic;
 SWITCHES_I : in std_logic_vector(7 downto 0);
 PSH_BUTTON : in std_logic;
 LEDS_O : out std_logic_vector (7 downto 0));
end top_system1;
architecture rtl of top_system1 is
signal DIR, DIR_REG,DATO,DATO_REG,DATO_RD : std_logic_vector (7 downto 0);
signal DIR_VLD, DATO_VLD,CE_RD : std_logic;
begin -- rtl
 
 DUT:entity work.cnt_epp
 port map (
 CLK => CLK,
 RST => RST,
 ASTRB => ASTRB,
 DSTRB => DSTRB,
 DATA => DATA,
 PWRITE => PWRITE,
 PWAIT => PWAIT,
 DATO_RD => DATO_RD,
 CE_RD => CE_RD,
 DIR => DIR,
 DIR_VLD => DIR_VLD,
 DATO => DATO,
 DATO_VLD => DATO_VLD);
 
end rtl;
V01.dat
V02.dat
gen_funciones.ucfNET "RELOJ" LOC = "L15"; 
# onBoard USB controller
 NET "ASTRB" LOC = "B9"; 
 NET "DSTRB" LOC = "A9"; 
 NET "PWRITE" LOC = "C15"; 
 NET "PWAIT" LOC = "F13"; 
 NET "DATA<0>" LOC = "A2"; 
 NET "DATA<1>" LOC = "D6"; 
 NET "DATA<2>" LOC = "C6"; 
 NET "DATA<3>" LOC = "B3"; 
 NET "DATA<4>" LOC = "A3"; 
 NET "DATA<5>" LOC = "B4"; 
 NET "DATA<6>" LOC = "A4"; 
 NET "DATA<7>" LOC = "C5"; 
# onBoard Pushbuttons
 NET "RST" LOC = "N4";
# DAC
NET "SYNC" LOC = "T3" ;
NET "D1" LOC = "R3" ;
NET "D2" LOC = "P6" ;
NET "SCLK" LOC = "N5" ;
top_system1.ucfNET "CLK" LOC = "L15"; 
# onBoard USB controller
 NET "ASTRB" LOC = "B9"; 
 NET "DSTRB" LOC = "A9"; 
 NET "PWRITE" LOC = "C15"; 
 NET "PWAIT" LOC = "F13"; 
 NET "DATA<0>" LOC = "A2"; 
 NET "DATA<1>" LOC = "D6"; 
 NET "DATA<2>" LOC = "C6"; 
 NET "DATA<3>" LOC = "B3"; 
 NET "DATA<4>" LOC = "A3"; 
 NET "DATA<5>" LOC = "B4"; 
 NET "DATA<6>" LOC = "A4"; 
 NET "DATA<7>" LOC = "C5"; 
# onBoard Pushbuttons
 NET "PSH_BUTTON" LOC = "F5"; 
 NET "RST" LOC = "N4";
# onBoard LEDS
 NET "LEDS_O<0>" LOC = "U18";
 NET "LEDS_O<1>" LOC = "M14";
 NET "LEDS_O<2>" LOC = "N14";
 NET "LEDS_O<3>" LOC = "L14";
 NET "LEDS_O<4>" LOC = "M13"; 
 NET "LEDS_O<5>" LOC = "D4"; 
 NET "LEDS_O<6>" LOC = "P16";
 NET "LEDS_O<7>" LOC = "N12";
# onBoard SWITCHES
 NET "SWITCHES_I<0>" LOC = "A10";
 NET "SWITCHES_I<1>" LOC = "D14";
 NET "SWITCHES_I<2>" LOC = "C14";
 NET "SWITCHES_I<3>" LOC = "P15";
 NET "SWITCHES_I<4>" LOC = "P12"; 
 NET "SWITCHES_I<5>" LOC = "R5"; 
 NET "SWITCHES_I<6>" LOC = "T5"; 
 NET "SWITCHES_I<7>" LOC = "E4";
cnt_dac.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cnt_dac is
 port (
 CLK : in std_logic;
 RST : in std_logic;
 DATO1 : in std_logic_vector(11 downto 0);
 DATO2 : in std_logic_vector(11 downto 0);
 DATO_OK : in std_logic;
 SYNC : out std_logic;
 SCLK : out std_logic;
 D1 : out std_logic;
 D2 : out std_logic);
end cnt_dac;
architecture RTL of cnt_dac is
 
begin -- RTL
 
 
end RTL;
cnt_dpram.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cnt_dpram is
 port (
 CLK : in std_logic;
 RST : in std_logic;
 DIR : in std_logic_vector (7 downto 0);
 DIR_VLD : in std_logic;
 DATO : in std_logic_vector (7 downto 0);
 DATO_VLD : in std_logic;
 ADDRESS : out std_logic_vector(7 downto 0);
 DATA : out std_logic_vector(11 downto 0);
 WE_DP1 : out std_logic;
 WE_DP2 : out std_logic);
end cnt_dpram;
architecture RTL of cnt_dpram is
 constant dir_dpram1 : std_logic_vector( 7 downto 0) := x"A1";
 constant dir_dpram2 : std_logic_vector( 7 downto 0) := x"A2";
 
begin -- RTL
end RTL;
cnt_epp.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity cnt_epp is
 port (
 CLK : in std_logic;
 RST : in std_logic;
 ASTRB : in std_logic;
 DSTRB : in std_logic;
 DATA : inout std_logic_vector(7 downto 0);
 PWRITE : in std_logic;
 PWAIT : out std_logic;
 DATO_RD : in std_logic_vector(7 downto 0);
 CE_RD : out std_logic;
 DIR : out std_logic_vector (7 downto 0);
 DIR_VLD : out std_logic;
 DATO : out std_logic_vector (7 downto 0);
 DATO_VLD : out std_logic);
end ;
architecture rtl of cnt_epp is
 
begin
end rtl;
DAC121S101.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DAC121S101 is
 port (
 VOUT : out real range 0.0 to 3.5;
 SYNC : in std_logic;
 SCLK : in std_logic;
 DIN : in std_logic);
end DAC121S101;
architecture rtl of DAC121S101 is
 signal dato_bin, reg_desp : std_logic_vector(15 downto 0) := (others => '0');
 signal cuenta : natural;
 constant tSCLK : time := 33 ns;
 constant tL, tH : time := 13 ns;
 constant tcs : time := 3 ns;
 constant tsud : time := 5 ns;
 constant tdhd : time := 4.5 ns;
 constant tSYNC : time := 20 ns;
 signal taux1, taux2 : time;
begin
-------------------------------------------------------------------------------
 -- verificación de tiempos
 
 assert not(taux1 -taux2 <= tSCLK)
 report "VIOLACIÓN DEL TIEMPO PERIODO DE SCLK(tCS)"
 severity error;
 
 process (SCLK)
 variable aux1, aux2 : time;
 begin
 if SCLK'event and SCLK = '0' then
 taux1 <= now;
 taux2 <= taux1;
 
 if SCLK = '1' then
 aux2 := aux1;
 aux1 := now;
 assert not(aux1-aux2 <= tL)
 report "VIOLACIÓN DEL TIEMPO A NIVEL BAJO DE SCLK (tL)"
 severity error;
 else
 aux2 := aux1;
 aux1 := now;
 assert not(aux1-aux2 <= tH)
 report "VIOLACIÓN DEL TIEMPO A NIVEL ALTO DE SCLK (tH)"
 severity error;
 end if;
 end if;
 end process;
 process (SYNC)
 variable aux6, aux7 : time;
 begin
 aux7 := aux6;
 aux6 := now;
 if SYNC'event and SYNC = '0' then
 assert not(aux6-aux7 <= tSYNC)
 report "VIOLACIÓN DE LA DURACIÓN DEL TIEMPO DEL NIVEL ALTO DE SYNC (tSYNC)"
 severity error; 
 end if;
 if SYNC'event and SYNC = '1' then
 if SCLK='0' then
 assert not(SCLK'last_event <= tcs)
 report "VIOLACIÓN DEL TIEMPO tCS"
 severity error;
 end if; 
 end if;
 
 end process;
 -----------------------------------------------------------------------------
 -- Modelado de funcionamiento.
 process (SCLK, SYNC)
 begin
 if SYNC = '1' then
 cuenta <= 0;
 reg_desp <= (others => '0');
 elsif SCLK'event and SCLK = '0' then
 if cuenta < 16 then
 cuenta <= cuenta+1;
 reg_desp <= reg_desp(14 downto 0)&DIN;
 end if;
 end if;
 end process;
 process (cuenta, SYNC, reg_desp)
 begin
 if SYNC = '0' then
 if cuenta = 16 then
 dato_bin <= reg_desp;
 end if;
 end if;
 end process;
 process (dato_bin, cuenta)
 begin -- process
 if cuenta = 16 then
 case dato_bin(15 downto 14) is
 when "00" =>
 VOUT <= real(to_integer(unsigned(dato_bin(11 downto 0))))*3.3/4096.0;
 when "11" =>
 VOUT <= 3.4;
 when others =>
 VOUT <= 0.0;
 end case;
 end if;
 end process;
end rtl;
dpram_mem.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram_mem is
 port (
 DIN : in std_logic_vector(11 downto 0);
 ADDR_IN : in std_logic_vector(7 downto 0);
 WE : in std_logic;
 CLK
: in std_logic;
 RST : in std_logic;
 ADDR_OUT : in std_logic_vector(7 downto 0);
 DOUT : out std_logic_vector(11 downto 0));
end entity;
architecture rtl of dpram_mem is
 
 
begin
 
 
end rtl;
epp_device.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity epp_device is
 port (
 DATA : inout std_logic_vector(7 downto 0);
 PWRITE : out std_logic;
 DSTRB : out std_logic;
 ASTRB : out std_logic;
 PWAIT : in std_logic);
end epp_device;
architecture sim of epp_device is
 constant T_clk_epp : time := 100 ns; -- Internal clock period. 
 signal clk_epp : std_logic := '0'; -- Internal clock signal. 
 signal read_value : std_logic_vector(7 downto 0) := (others => '0');
constant dir_frec : std_logic_vector( 7 downto 0) := x"F0";
 constant dir_dpram1 : std_logic_vector( 7 downto 0) := x"A1";
constant dir_dpram2 : std_logic_vector( 7 downto 0) := x"A2";
 constant EPP_cicle_length : natural := 10;
begin
 -- internal clock signal generation.
 clk_epp <= not(clk_epp) after T_clk_epp/2;
 process
 procedure epp_cycle ( address : in std_logic_vector(7 downto 0);
 data_io : inout std_logic_vector(7 downto 0);
 r_w : in character) is
 
 begin
 wait until clk_epp = '1';
 PWRITE <= '0';
 wait until clk_epp = '1';
 ASTRB <= '0';
 data <= address;
 wait for T_clk_epp*EPP_cicle_length;
 ASTRB <= '1';
 wait until clk_epp = '1';
 data <= (others => 'Z');
 PWRITE <= '1';
 wait until clk_epp = '1';
 wait for T_clk_epp*EPP_cicle_length;
-------------------------------------------------------------------------------
 if r_w = 'w' then -- write cicle 
 PWRITE <= '0';
 data <= data_io;
 end if;
-------------------------------------------------------------------------------
 wait until clk_epp = '1';
 DSTRB <= '0';
 wait for T_clk_epp*EPP_cicle_length;
 if r_w = 'r' then
 data_io:= data;
 end if;
 DSTRB <= '1';
 wait until clk_epp = '1';
 data <= (others => 'Z');
 PWRITE <= '1';
 wait until clk_epp = '1';
 end procedure;
 variable dato : std_logic_vector(7 downto 0);
 variable dir : std_logic_vector(7 downto 0);
 begin
 --inicialización 
 data <= (others => 'Z');
 PWRITE <= '1';
 DSTRB <= '1';
 ASTRB <= '1';
 dir := (others => '0');
 wait for 130 ns;
 -- ciclos de lectura/escritura
 
 report "FIN CICLO R/W" severity failure;
 end process;
end sim;
gen_dir.vhdlibrary ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gen_dir is
 port (
 CLK : in std_logic;
 RST : in std_logic;
 DIR : in std_logic_vector (7 downto 0);
 DIR_VLD : in std_logic;
 DATO : in std_logic_vector (7 downto 0);
 DATO_VLD : in std_logic;
 ADDR_OUT : out std_logic_vector(7 downto 0);
 DATO_OK : out std_logic);
end gen_dir;
architecture rtl of gen_dir is
 constant dir_frec : std_logic_vector( 7 downto 0) := x"F0";
 constant T_DAC : integer := 68; --pulsos dura la conversion mínima
 
begin
 end rtl;
gen_funciones.vhdlibrary ieee;
use ieee.std_logic_1164.all;
entity gen_funciones is
 port (
 RELOJ : in std_logic;
 RST : in std_logic;
 -- PUERTO EPP
 ASTRB : in std_logic;
 DSTRB : in std_logic;
 DATA : inout std_logic_vector(7 downto 0);
 PWRITE : in std_logic;
 PWAIT : out std_logic;
 -- DAC
 SYNC : out std_logic;
 SCLK : out std_logic;
 D1 : out std_logic;
 D2 : out std_logic);
end gen_funciones;
architecture rtl of gen_funciones is
 
 signal CLK : std_logic;
--SEÑALES DEL CONTROLADOR EPP--
 signal DIR : std_logic_vector (7 downto 0);
 signal DIR_VLD : std_logic;
 signal DATO : std_logic_vector (7 downto 0);
 signal DATO_VLD : std_logic;
 signal DATO_RD : std_logic_vector (7 downto 0);
 signal CE_RD : std_logic;
--SEÑALES DEL CONTROLADOR DPRAM--
 signal ADDRESS : std_logic_vector(7 downto 0);
 signal DATA_DP : std_logic_vector (11 downto 0); 
 signal WE_DP1 : std_logic;
 signal WE_DP2 : std_logic;
--SEÑALES DE LAS MEMORIAS DPRAM--
 signal DATO1 : std_logic_vector (11 downto 0);
 signal DATO2 : std_logic_vector (11 downto 0);
--SEÑALES DE GENERADOR DE _DIRECCIONES--
 signal ADDR_OUT : std_logic_vector(7 downto 0);
 signal DATO_OK : std_logic;
begin -- rtl
 
U_dcm :entity work.dcm
 port map
 (CLK_IN => RELOJ, 
 CLK_OUT => CLK,
 RESET => RST); 
 
 
 U_cnt_epp:entity work.cnt_epp
 port map (
 CLK => CLK,
 RST => RST,
 ASTRB => ASTRB,
 DSTRB => DSTRB,
 DATA => DATA,
 PWRITE => PWRITE,
 PWAIT => PWAIT,
 DATO_RD => DATO_RD,
 CE_RD => CE_RD,
 DIR => DIR,
 DIR_VLD => DIR_VLD,
 DATO => DATO,
 DATO_VLD => DATO_VLD);
 
 U_cnt_dpram:entity work.cnt_dpram
 port map (
 CLK => CLK,
 RST => RST,
 DIR => DIR,
 DIR_VLD => DIR_VLD,
 DATO => DATO,
 DATO_VLD => DATO_VLD,
 ADDRESS => ADDRESS,
 DATA => DATA_DP,
 WE_DP1 => WE_DP1,
 WE_DP2 => WE_DP2);
 
 U_dpram_mem1 : entity work.dpram_mem
 port map (
 DIN => DATA_DP,
 ADDR_IN => ADDRESS,
 WE => WE_DP1,
 CLK => CLK,
 RST => RST,
 ADDR_OUT => ADDR_OUT,
 DOUT => DATO1);
 
 U_dpram_mem2 : entity work.dpram_mem
 port map (
 DIN => DATA_DP,
 ADDR_IN => ADDRESS,
 WE => WE_DP2,
 CLK => CLK,
 RST => RST,
 ADDR_OUT => ADDR_OUT,
 DOUT => DATO2);
 U_gen_dir:entity work.gen_dir
 port map (
 CLK => CLK,
 RST => RST,
 DIR => DIR,
 DIR_VLD => DIR_VLD,
 DATO => DATO,
 DATO_VLD => DATO_VLD,
 ADDR_OUT => ADDR_OUT,
 DATO_OK => DATO_OK);
 
 U_cnt_dac :entity work.cnt_dac
 port map (
 CLK => CLK,
 RST => RST,
 DATO1 => DATO1,
 DATO2 => DATO2,
 DATO_OK => DATO_OK,
 SYNC => SYNC,
 SCLK => SCLK,
 D1 => D1,
 D2 => D2);
end rtl;
DAC121S101.pdf
DAC121S101/DAC121S101Q
February 19, 2010
12-Bit Micro Power, RRO Digital-to-Analog Converter
General Description
The DAC121S101 is a full-featured, general purpose 12-bit
voltage-output digital-to-analog converter (DAC) that can op-
erate from a single +2.7V to 5.5V supply and consumes just
177 µA of current at 3.6 Volts. The on-chip output amplifier
allows rail-to-rail output swing and the three wire serial inter-
face operates at clock rates up to 30 MHz over the specified
supply voltage range and is compatible with standard SPI™,
QSPI, MICROWIRE and DSP interfaces. Competitive de-
vices are limited to 20 MHz clock rates at supply voltages in
the 2.7V to 3.6V range.
The supply voltage for the DAC121S101 serves as its voltage
reference, providing the widest possible output dynamic
range. A power-on reset circuit ensures that the DAC output
powers up to zero volts and remains there until there is a valid
write to the device. A power-down feature reduces power
consumption to less than a microWatt.
The low power consumption and small packages of the
DAC121S101 make it an excellent choice for use in battery
operated equipment.
The DAC121S101 is a direct replacement for the AD5320 and
the DAC7512 and is one of a family of pin compatible DACs,
including the 8-bit DAC081S101 and the 10-bit DAC101S101.
The DAC121S101 operates over the extended industrial tem-
perature range of −40°C to +105°C while the DAC121S101Q
operates over the
Grade 1 automotive temperature range of
−40°C to +125°C. The DAC121S101 is available in a 6-lead
TSOT and an 8-lead MSOP and the DAC121S101Q is avail-
able in the 6-lead TSOT only.
Features
■ DAC121S101Q is AEC-Q100 Grade 1 qualified and is
manufactured on an Automotive Grade Flow.
■ Guaranteed Monotonicity
■ Low Power Operation
■ Rail-to-Rail Voltage Output
■ Power-on Reset to Zero Volts Output
■ Wide Temperature Range of −40°C to +125°C
■ Wide Power Supply Range of +2.7V to +5.5V
■ Small Packages
■ Power Down Feature
Key Specifications
■ Resolution 12 bits
■ DNL +0.25, -0.15 LSB (typ)
■ Output Settling Time 8 µs (typ)
■ Zero Code Error 4 mV (typ)
■ Full-Scale Error −0.06 %FS (typ)
■ Power Consumption
■ — Normal Mode 0.64mW (3.6V) / 1.43mW (5.5V) typ
— Pwr Down Mode 0.14µW (3.6V) / 0.39µW (5.5V) typ
Applications
■ Battery-Powered Instruments
■ Digital Gain and Offset Adjustment
■ Programmable Voltage & Current Sources
■ Programmable Attenuators
■ Automotive
Pin Configuration
20114901 20114902
SPI™ is a trademark of Motorola, Inc.
© 2010 National Semiconductor Corporation 201149 www.national.com
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Ordering Information
Order Numbers Temperature Range Package Top Mark Feature
DAC121S101CIMM −40°C ≤ TA ≤ +105°C MSOP
X60C 
DAC121S101CIMMX −40°C ≤ TA ≤ +105°C MSOP T/R
DAC121S101CIMK −40°C ≤ TA ≤ +105°C TSOT
X61C 
DAC121S101CIMKX −40°C ≤ TA ≤ +105°C TSOT T/R
DAC121S101QCMK −40°C ≤ TA ≤ +125°C TSOT
X61Q
AEC-Q100 Grade 1
Qualified; Automotive
Grade Production FlowDAC121S101QCMKX −40°C ≤ TA ≤ +125°C TSOT T/R
DAC121S101EVAL Evaluation Board TSOT 
Block Diagram
20114903
Pin Descriptions
TSOT
(SOT-23)
Pin No.
MSOP
Pin No.
Symbol Description
1 4 VOUT DAC Analog Output Voltage.
2 8 GND Ground reference for all on-chip circuitry.
3 1 VA Power supply and Reference input. Should be decoupled to GND.
4 7 DIN
Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK
after the fall of SYNC.
5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
6 5 SYNC
Frame synchronization input for the data input. When this pin goes low, it enables the input
shift register and data is transferred on the falling edges of SCLK. The DAC is updated on
the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
 2, 3 NC No Connect. There is no internal connection to these pins.
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A.C. and Timing Characteristics
The following specifications apply for VA = +2.7V to +5.5V, RL = 2kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 48 to 4047. Boldface limits apply for TMIN ≤ TA ≤ TMAX: all other limits TA = 25°C, unless otherwise specified.
Symbol Parameter Conductions Typical Limits
Units
(Limits)
fSCLK SCLK Frequency 30 MHz (max)
ts
Output Voltage Settling Time
(Note 10)
400h to C00h code
change, RL = 2kΩ
CL ≤ 200 pF 8 10 µs (max)
CL = 500 pF 12 µs
00Fh to FF0h code
change, RL = 2kΩ
CL ≤ 200 pF 8 µs
CL = 500 pF 12 µs
SR Output Slew Rate 1 V/µs
 Glitch Impulse Code change from 800h to 7FFh 12 nV-sec
 Digital Feedthrough 0.5 nV-sec
tWU Wake-Up Time
VA = 5V 6 µs
VA = 3V 39 µs
1/fSCLK SCLK Cycle Time 33 ns (min)
tH SCLK High time 5 13 ns (min)
tL SCLK Low Time 5 13 ns (min)
tSUCL
Set-up Time SYNC to SCLK Rising
Edge
 −15 0 ns (min)
tSUD Data Set-Up Time 2.5 5 ns (min)
tDHD Data Hold Time 2.5 4.5 ns (min)
tCS SCLK fall to rise of SYNC
VA = 5V 0 3 ns (min)
VA = 3V −2 1 ns (min)
tSYNC SYNC High Time
2.7 ≤ VA ≤ 3.6 9 20 ns (min)
3.6 ≤ VA ≤ 5.5 5 10 ns (min)
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Transfer Characteristic
20114905
FIGURE 1. Input / Output Transfer Characteristic
Timing Diagram
20114906
FIGURE 2. DAC121S101 Timing
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1.0 Functional Description
1.1 DAC SECTION
The DAC121S101 is fabricated on a CMOS process with an
architecture that consists of switches and a resistor string that
are followed by an output buffer. The power supply serves as
the reference voltage. The input coding is straight binary with
an ideal output voltage of:
VOUT = VA x (D / 4096)
where D is the decimal equivalent of the binary code that is
loaded into the DAC register and can take on any value be-
tween 0 and 4095.
1.2 RESISTOR STRING
The resistor string is shown in Figure 3. This string consists
of 4096 equal valued resistors with a switch at each junction
of two resistors, plus a switch to ground. The code loaded into
the DAC register determines which switch is closed, connect-
ing the proper node to the amplifier. This configuration guar-
antees that the DAC is monotonic.
20114907
FIGURE 3. DAC Resistor String
1.3 OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an
output voltage range of 0V to VA. All amplifiers, even rail-to-
rail types, exhibit a loss of linearity as the output approaches
the supply rails (0V and VA, in this case). For this reason,
linearity is specified over less than the full output range of the
DAC. The output capabilities of the amplifier are described in
the Electrical Tables.
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs. See the Timing Diagram
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the DIN line is clocked into the 16-
bit serial input register on the falling edges of SCLK. On the
16th falling clock edge, the last data bit is clocked in and the
programmed function (a change in the mode of operation and/
or a change in the DAC register contents) is executed. At this
point the SYNC line may be kept low or brought high. In either
case, it must be brought high for the minimum specified time
before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and DIN buffers draw more current when they
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register, Figure 4, has sixteen bits. The first
two bits are "don't cares" and are followed by two bits that
determine the mode of operation (normal mode or one of
three power-down modes). The contents of the serial input
register are transferred to the DAC register on the sixteenth
falling edge of SCLK. See Timing Diagram, Figure 2.
20114908
FIGURE 4. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the shift register is reset and the write sequence
is invalid. The DAC register is not updated and there is no
change in the mode of operation or in the output voltage.
www.national.com 14
D
A
C
1
2
1
S
1
0
1
/D
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C
1
2
1
S
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1
Q
	DAC121S101/DAC121S101Q
	General Description
	Features
	Key Specifications
	Applications
	Pin Configuration
	Ordering Information
	Block Diagram
	Pin Descriptions
	Absolute Maximum Ratings
	Operating Ratings (Note 1, Note 2)
	Package Thermal Resistances
	Electrical Characteristics
	A.C. and Timing Characteristics
	Specification Definitions
	Transfer Characteristic
	FIGURE 1. Input / Output Transfer Characteristic
	Timing Diagram
	FIGURE 2. DAC121S101 Timing
	Typical Performance Characteristics
	1.0 Functional Description
	1.1 DAC SECTION
	1.2 RESISTOR STRING
	FIGURE 3. DAC Resistor String
	1.3 OUTPUT AMPLIFIER
	1.4 SERIAL INTERFACE
	1.5 INPUT SHIFT REGISTER
	FIGURE 4. Input Register Contents
	1.6 POWER-ON RESET
	1.7 POWER-DOWN MODES
	TABLE 1. Modes of Operation
2.0 Applications Information
	2.1 DSP/MICROPROCESSOR INTERFACING
	2.1.1 ADSP-2101/ADSP2103 Interfacing
	FIGURE 5. ADSP-2101/2103 Interface
	2.1.2 80C51/80L51 Interface
	FIGURE 6. 80C51/80L51 Interface
	2.1.3 68HC11 Interface
	FIGURE 7. 68HC11 Interface
	2.1.4 Microwire Interface
	FIGURE 8. Microwire Interface
	2.2 USING REFERENCES AS POWER SUPPLIES
	2.2.1 LM4130
	FIGURE 9. The LM4130 as a power supply
	2.2.2 LM4050
	FIGURE 10. The LM4050 as a power supply
	2.2.3 LP3985
	FIGURE 11. Using the LP3985 regulator
	2.2.4 LP2980
	FIGURE 12. Using the LP2980 regulator
	2.3 BIPOLAR OPERATION
	FIGURE 13. Bipolar Operation
	TABLE 2. Some Rail-to-Rail Amplifiers
	2.4 LAYOUT, GROUNDING, AND BYPASSING
	Physical Dimensions
PmodDA1.pdf
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www.digi lent inc.com 
Revision: 04/12/05 
 
215 E Main Suite D | Pullman, WA 99163 
(509) 334 6306 Voice and Fax 
 
Doc: 502-063 page 1 of 1 
 
Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. 
Overview 
 
The Digilent PmodAD1 Digital to Analog 
Module Converter module (the DA1™) 
converts signals from digital to analog at up to 
one MSa per second. The DA1 uses a 6-pin 
header connector and at less than one square 
inch is small enough to be located where the 
reconstructed signal is needed. 
 
Features include: 
 
• two AD7303 8-bit D/A converter chips 
that convert up to one MSa per second 
• a 6-pin header and 6-pin connector 
• four D/A conversion channels 
• very low power consumption 
• small form factor (0.80” x 0.80”). 
 
Functional Description 
 
The DA1 can produce an analog output 
ranging from 0-3.3 volts. It has four 
simultaneous D/A conversion channels, each 
with an 8-bit converter that can process 
separate digital signals. 
 
The DA1 is equipped with two AD7303 digital 
to analog converters. Each converter has two 
channels through which digital signals can be 
converted to analog signals. 
 
Outputs are produced by sending commands 
via the SPI/MICROWIRE™ serial bus to the 
D/A converters. The two converters are 
connected in parallel so that commands are 
sent to both converters simultaneously. 
 
The DA1 is designed to work with Digilent 
system boards. Some system boards, like the 
Digilent Pegasus board, have a 6-pin header 
that can be connected to the DA1’s 6-pin 
header using a 6-pin cable. 
Other Digilent boards may need a Digilent 
Modular Interface Board (MIB) and a 6-pin 
cable to connect to the DA1. The MIB plugs 
into the system board and the cable connects 
the MIB to the DA1. 
 
The DA1 can be powered by voltage from 
either a Digilent system board or an outside 
device. Damage can result if power is supplied 
from both sources or if the outside device 
supplies more than 3V. For more information, 
see www.digilentinc.com. 
 
For information on the AD7303, see the Analog 
Devices data sheet at www.analog.com. 
 GND
 VCC
DA1 Circuit Diagram
AD7303
D/A
Converter
AD7303
D/A
Converter
D2
D1
2 Sync,
Clock
Analog Outputs
J1
 C
on
ne
ct
or
J2
 C
on
ne
ct
or